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work1
- 实现序列检测器的功能，检验序列代码是否正确，给出说明。-Detector to achieve the function of sequence to test serial code is correct, given instructions.
matlab
- 仿真程序：首先需要用一个随机发生器产生（0.1）内的均匀随机数，然后再将该序列映射到对应的幅度电平｛Am｝。然后将这个范围再分成4个相等的区间，这些子区间分别对应于4个信号比特的符号00，01，10，11。检测器观察到r=Am+n，并且计算r和4种可能传输的信号幅度之间的距离，它的输出Bm就是相应于最小距离的信号电平。Bm与真正的的传输信号幅度比较，差错计数器用来对检测器产生的差错计数。-Simulation program: first need to use a random genera
detect
- 基于QuartusII的序列检测器，可下载到实验箱-Based on the sequence QuartusII detector, can be downloaded to test me
DS-CDMA-with-PASTd-MUD-with-m-DS
- DS-CDMA链路中加入基于子空间的PASTd多用户检测方法。系统中采用m序列阔频，可以通过高斯信道或瑞利信道。可以直接运行得到不同信噪比下的误码率曲线。-DS-CDMA link added Subspace-based multiuser detector PASTd. M sequence used in the system wide-band, Gaussian channel, or by Rayleigh channel. Get different signal to noise
Program2
- 将8位待测预置数作为外部输入信号，即可以随时改变序列检测器中的比较数据。写出此程序的符号化单进程有限状态机。-The 8-bit pre-measured as the number of external input signal, which can change at any time in the sequence comparison of the data detector. Write the symbol of this process a single process fini
VHDL
- 1、根据设计要求，完成对序列信号检测器的设计。 2、进一步加强对QuartusⅡ的应用和对VHDL语言的使用。-1, according to design requirements, to complete the sequence of the signal detector design. 2, to further strengthen the Quartus Ⅱ applications and the use of the VHDL language.
sequential-detactor
- 本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA code and simulation.
EDA1
- 用VHDL编程实现序列信号发生器与检测器设计和数字钟设计-VHDL programming sequence signal generator and detector design and the design of the digital clock
main-dc
- New Positive sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions
01712059
- New Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions
check
- 这是一个检测器，功能是可以检测输入信号里面“1111”序列的vhdl程序。-This is a detector, the function is the sequence of " 1111" of the input signal which can be detected vhdl procedures.
EDAexp4
- FPGA环境下，用VHDL语言实现序列脉冲器和检测器。-FPGA environment, the use of the VHDL sequence of pulses and detector.
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
Matlab-Source-Codes
- Generation of ASK: Amplitude shift keying - ASK - in the context of digital communication is a modulation process which imparts to a sinusoid two or more discrete amplitude levels 1. These are related to the number of levels adopted by the digit
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident
test-16QAM
- 基于Matlab的Coherent 16QAM simulation。包括产生伪随机比特序列、产生电脉冲序列、NRZ调制、AWGN 信道 plot_opti_spec、平衡探测器、均衡等。-Matlab-based Coherent 16QAM simulation. Comprises generating pseudo-random bit sequence, generating an electrical pulse sequence, NRZ modulation, AWGN chan
BKM
- 设计一个11位巴克码序列峰值检测器，巴克码序列为11’b 11100010010。要求 能够检测巴克码序列峰值； 在存在1bits错误情况下，能够检测巴克码序列峰值。 写出测试仿真程序-Design of a 11 Barker code sequence peak detector, Barker code sequence 11 b 11100010010. Claim Barker code sequence can be detected peak 1bits in
small
- 根据相机的指向数据，实现对亮星星表9110颗星在探测器上的模拟投影，得到序列星图-According to the data of the camera, to achieve the Bright Star Catalogue 9110 stars on the detector simulation projection to obtain sequence star map
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b